1. Field of the Invention
The present invention generally relates to lithographic processes for manufacture of semiconductor integrated circuits and, more particularly, to production of assist features on lithographic reticles and masks.
2. Description of the Prior Art
The potential for improved performance and functionality of integrated circuits as well as potentially increased manufacturing economy has led to designs utilizing extremely small feature size regimes and much increased integration density. While numerous advances in semiconductor technology have allowed electronic devices to be fabricated at smaller sizes and in increased numbers and proximity on a chip while maintaining electrical characteristics, many gains in integration density have been achieved through scaling of existing device designs to smaller sizes, implying reduced dimensions of components of devices (e.g. gate insulator thicknesses and channel lengths and widths), operation at lower voltages and the like.
While semiconductor processing techniques have become very sophisticated and allow fabrication of some structures much smaller than can be resolved in a lithographic exposure, the location and basic dimensions of any device in an integrated circuit must be patterned lithographically. Therefore, lithographic resolution of a given exposure tool generally limits the integration density and minimum feature size that can be achieved. Conversely, lithographic exposures for integrated circuit manufacture generally include features which approach resolution limits of the exposure tool. For this reason, different exposure media (e.g. I-line, deep ultra-violet light, electron beams and X-rays have been used to increase available resolution. Further, masks have been developed including so-called assist features in order to enhance resolution.
For example, one known assist feature employs varying thickness of transparent features to cause phase shift in the light used to illuminate regions of the target such that an interference pattern is developed. The interference pattern causes increased rate of change of exposure dose at the perimeter of features to allow features to be exposed with enhanced sharpness and resolution.
Another image enhancement technique is off-axis illumination (OAI) which functions by excluding exposure illumination from the center of the pupil and thus emphasizes the aerial image information toward the edges of the pupil. OAI can be used to enhance the resolution and depth of focus process latitude for arrays of closely nested patterns. Isolated patterns are often not enhanced by OAI. As a result, it is often desirable to place sub-resolution assist features (SRAF) adjacent to isolated product patterns. These SRAF structures enhance the process latitude for isolated features by making them behave like nested features in the exposure process while the SRAF are too small to actually form a separate pattern on the substrate.
To achieve high integration density, it is necessary to place connections at different levels in the integrated circuit structure than the levels at which active or passive devices are formed. Therefore, connections to the devices are generally made vertically through contact holes to respective portions (e.g. gate, source and drain) of each device. Contact holes may also be used to make connections between wiring layers. However, known resolution enhancement techniques are only applicable to singular small features such as contact holes to allow scaling of contacts as the devices themselves are scaled to smaller sizes with substantial difficulty in reticle formation and with limited success.
More specifically, attempts to provide assist features have presented several problems. For example, assist features must, by their nature, generally be quite small (to prevent printing of the assist feature, while enhancing resolution of the intended feature) and often ideally less than the minimum feature size of the ground rules of the integrated circuit design being fabricated. While such reduced sizes are possible through demagnification of the mask pattern during lithographic exposures (except for the use of X-rays where a contact mask must be employed), formation of assist features of ideal size and placement in a mask may compromise reliability of manufacture of the mask, itself, leading to a likelihood of increased costs due to loss of mask manufacturing yield.
Perhaps more importantly, approaches using numerous discrete assist features, such as an array of mask apertures to create a contact hole, that have been employed, provide resolution of images which is of less than desired quality since resolution increases with the number of assist features but the number of assist features is generally limited by practical considerations. For example, the number of assist features which must be separately written to the mask greatly increases mask pattern writing time and thus increases mask costs. Further, the data involved may approach or exceed mask writer capacity. Moreover, the area required for such assist features may also exceed the area that can be accommodated in masks for devices having very high integration density since features that may not be substantially nested may still be sufficiently proximate that the areas ideally required for SRAF structures may overlap or interact.
Thus, assist features comprising arrays of mask apertures can only be used to form a contact hole where the contact hole is isolated from other features. Accordingly, the use of conventional assist features for production of contact holes may severely complicate integrated circuit layout and is not applicable to the majority of circumstances where contact holes are needed (e.g. to contact different parts of, for example, a transistor of small dimensions).
It is therefore an object of the present invention to provide an assist feature of small footprint in a mask which is capable of scaling contact holes to sizes comparable to feature sizes obtainable with optical lithography.
It is another object of the invention to provide a method of making a mask including assist features which are of reduced footprint and provide improved contact hole exposures.
It is a further object of the present invention to provide reduction of pattern data and lithographic writing time in reticle manufacture.
In order to accomplish these and other objects of the invention, an exposure pattern for a mask feature for lithographic patterning of a contact hole is provided comprising an illuminated annulus having a sub-resolution width including an inner edge for producing an intermediate level of illumination in a pattern area and an outer edge for producing an intermediate level of illumination of an assist feature separated from said pattern area. The assist feature may surround a pattern area such as a contact hole or be adjacent an elongated side of an elongated feature or between adjacent elongated features. The sub-resolution assist features may be provided for all or less than all pattern areas or even one or more particular portions of a pattern area.
In accordance with another aspect of the invention, a method of making a lithographic mask is provided including steps of exposing a hybrid resist with an annular pattern having sub-resolution width, and developing the hybrid resist to form openings corresponding to a pattern area and an assist feature spaced from the pattern area.
In accordance with a further aspect of the invention, a method of forming an integrated circuit is provided including steps of exposing a resist with a pattern including a feature corresponding to a pattern area of approximately minimum feature size and a sub-lithographic assist feature formed using a hybrid resist spaced therefrom and completing the integrated circuit.